? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? standard low profile converters with optional velocity output signal and reference input: - internal transformer isolation - all common l-l levels and frequencies accuracy: 10 bit: 21 minutes 12 bit: 8.5 minutes 14 bit: 4 minutes, 0.9 lsb or 2.6 minutes (high accuracy) logic: - ttl compatible - parallel binary angle output power required: 15 vdc and +5 vdc for new designs see ddc sdc-630/632/634*a/st series description the sdc-630/632/634 series are low cost, low profile synchro-to- digital (s/d) and resolver-to-digital (r/d) tracking converters with standard pin configurations. they use a unique control transformer algorithm that provides inherently higher accuracy and jitter-free out- put. utilizing a type ii servo loop, these converters have no velocity lag up to the specified tracking rate, and output data is always fresh and continuously available. each unit is fully trimmed and requires no adjustment or field calibration. applications these converters may be used wherever analog angle data from a synchro or resolver must be rapidly and accurately converted to digi- tal form for transmission, storage or analysis. because these units are extremely rugged and stable, and meet the requirements on mil- std-202e, they are suitable for the most severe industrial, commer- cial and military applications. military ground support and avionics uses include ordnance control, radar tracking systems, navigation and collision avoidance systems. sdc-630/632/634* 10-, 12-, 14-bit synchro-to-digital or resolver-to-digital converter make sure the next card you purchase has... ? 1993, 1999 data device corporation all trademarks are the property of their respective owners. * patented
2 data device corporation www.ddc-web.com sdc-630/632/634 h-07/05-0 figure 1. sdc-630/632/634 block diagram scott-t solid state resolver transformer buffer resolver input option synchro input option s1 sin sin sin sin bit 1 bit 1 (msb) bit 10,12, or 14 (lsb) bit 10, 12 or 14 rh ref rl sin cos cos t cos input reference vel velocity (optional) inh inhibit cb converter busy input options solid state controlled oscillator voltage and processor error isolation control up-down counter (contains angle ) (ct) transformer transformer demodulator option cos ( ( ?) ?) s1 s2 s2 s3 s3 s4
3 data device corporation www.ddc-web.com sdc-630/632/634 h-07/05-0 table 1. sdc-630/632/634 specifications (apply over temperature range, power supply range, reference fre- quency and amplitude range, 10% signal amplitude variation, and up to 10% harmonic distortion in the reference.) parameter value sdc-630 sdc-632 sdc-634 resolution 10 bits 12 bits 14 bits accuracy standard units high accuracy option 21 min ? 8.5 min ? 4 min 0.9 lsb 2.6 min signal and reference input synchro input* 90v l-l, 400 hz (option h) 90v l-l, 60 hz (option i) 11.8v l-l, 400 hz (option l) resolver input* 90v l-l, 400 hz (option h) 26v l-l, 400 hz (option m) 11.8v l-l, 400 hz (option l) 350-1000 hz 47-1000 hz 350-1000 hz 350-1000 hz 350-1000 hz 350-1000 hz signal input impedance (l-l balanced, resistive) 148 k ? min 148 k ? min 19 k ? min 198 k ? min 57 k ? min 26 k ? min reference input* options h, i options m, l reference voltage range reference input impedance (resistive) 40-150 vrms 10-50 vrms 300 k ? min 80 k ? min *transformer isolated. other voltages and frequencies available on special order. digital input/outputs logic type inhibit input (inh) loading outputs type 10, 12, or 14 parallel data bits converter busy (cb) drive capability ttl logic ?0? inhibits 0.2 std. ttl loads plus 18 k ? min pull-up resistor to +5v supply low power schottky (can drive remote loads) natural binary angle; positive logic 0.5 to 1.5 sec positive pulse. data changes on leading edge. 2 std. ttl loads velocity output (on special order only) type voltage range scale factor (for sdc-634 - others on request) options h, m, and l option i derived from an op-amp with low impedance output. positive output for increasing angle 10v min 6v per rps nominal (10v = 15 rps) 3.3v per rps nominal (10v = 2.7 rps) table 1. sdc-630/632/634 specifications (cont.) (apply over temperature range, power supply range, reference fre- quency and amplitude range, 10% signal amplitude variation, and up to 10% harmonic distortion in the reference.) parameter value power supplies nominal voltage voltage range maximum voltage without damage current sdc-630 (632) t ypical maximum sdc-634 typical maximum +15 v supply -15 v supply +5 v supply +11 to +16.5 v +18 v 8 ma (4) 13 ma (6) 10 ma 15 ma -11 to -16.5 v -18 v 18 ma (18) 30 ma (30) 20 ma 30 ma +4.5 to +5.5 v +7 v 80 ma (80) 120 ma (120) 100 ma 150 ma temperature ranges operating -1 option -3 option storage -55c to +105c 0c to +70c -55c to +125c physical characteristics size (encapsulated module) weight 3.125 x 2.625 x 0.43 inches (7.94 x 6.67 x 1.07 cm) 4 oz (113 gm.) signal frequency range dynamic characteristics input rate for full accuracy (min range) options h, m, l (400 hz) option i (60 hz) acceleration for 1 lsb lag options h, m, l (400 hz) option i (60 hz) settling time for normal tracking (up to specified input rate) for 179 step change (typical values) options h, m, l (400 hz) settling to 1 lsb settling to final value option i (60 hz) settling to 1 lsb settling to final value velocity constant (type ii servo loop) acceleration constant (nominal values) options h, m, l (400 hz) option i (60 hz) min typ min typ min typ 0-22 rps 40 0-8 rps 10 12,600/sec 2 typ 770/sec 2 typ no lag error 80 msec 100 msec 300 msec 500 msec k v = k a =36,000sec 2 k a =2,200sec 2 0-40 rps 50 0-10 rps 12.5 4500/sec 2 typ 295/sec 2 typ no lag error 90 msec 110 msec 300 msec 360 msec k v = k a =54,000sec 2 k a =3,600sec 2 0-10 rps 15 0-1.25 rps 3 610/sec 2 typ 20/sec 2 typ no lag error 150 msec 200 msec 800 msec 1000 msec k v = k a =27,800sec 2 k a =900sec 2
4 data device corporation www.ddc-web.com sdc-630/632/634 h-07/05-0 technical information timing figure 2 shows the timing waveforms of the converter. whenever an input angle change occurs, the converter changes the digital angle in steps of 1 lsb, and generates a converter busy impulse (cb). the cb is a positive pulse 0.5 to 1.5sec long. data changes on the leading edge of the cb pulse, and data can be transferred 0.5sec after the leading edge. the simplest method of interfacing with a computer is to transfer data at a fixed time interval after the inhibit is applied. the con- verter will ignore an inhibit applied during the ?busy? interval until that interval is over. timing is as follows: (a) apply the inhibit, (b) wait 0.5sec, (c) transfer the data, and (d) release the inhibit. extra cb pulses will not occur if the input angle changes while the counter is locked by the inh. valid 6.1 s min depends on d dt 0.5-1.5 s .5 s data valid inhibit (inh) "1" "0" converter busy (cb) "1" "0" figure 2. sdc-630/632/634 timing diagram dynamic performance a type ii servo loop (kv = ) and very high acceleration con- stants give these converters superior dynamic performance, as listed in the specifications. if the power supply voltages are not the +15 vdc nominal values, the specified input rates for full accuracy will increase or decrease in proportion to the fractional change in voltage. the +15 v supply voltage will determine the positive maximum velocity, and the -15 v supply voltage will determine the negative maximum velocity. so long as the maximum tracking rate is not exceeded, there will be no lag in the converter output. if a step input occurs, as is like- ly when the power is initially turned on, the response will be crit- ically damped. figure 3 shows the response to a step input. after initial slewing at the maximum tracking rate of the convert- er, there is one overshoot which is inherent to a type ii servo. the overshoot settling to a final value is a function of the small signal settling time. power supplies the main power supplies can vary over their specified ranges with no change in the converter specifications except for a pro- portional change in the maximum tracking rates. when testing or evaluating the converters, it is advisable to limit the current to each of the three power supplies. set each limit to 50% greater than the maximum current listed for that supply in the specifications table. transformer input to prevent damage to the input transformers, the maximum steady state voltage should not exceed the specified input volt- age by more than 30%. the maximum common mode voltage (dc plus recurrent ac peak) should not exceed 500 v. sdc-630 400 hz a 190 sec -1 b 91 sec -1 60 hz a 46 sec -1 b 23 sec -1 sdc-632 226 sec -1 100 sec -1 58 sec -1 26 sec -1 sdc-634 167 sec -1 56 sec -1 30 sec -1 10 sec -1 overshoot small signal settling time max slope equals tracking rate ( slew rate ) 2 1 figure 3. response to a step input a 2 ( +1) g = s 2 ( +1) s b s 10b the nominal open loop transfer function is given by where the parameters a and b are: table 2. transfer function parameters
5 data device corporation www.ddc-web.com sdc-630/632/634 h-07/05-0 accommodating non-standard input voltages the signal and reference input levels of the sdc-630 series can be resistively scaled to accommodate non-standard voltages. a converter should be selected that is the next lower standard volt- age and the voltage is then scaled up with resistors in series with the synchro and/or reference inputs. for a synchro input (sdc), a resistor r sig is added in series with s1, s2 and s3, which is determined as follows: r sig = 1.11k (new l-l voltage - standard unit voltage) that is, 1.11k for each volt above that for which the standard unit is designed. example: an sdc-634-l (11.8v) is to be used at 50v l-l. r sig = 1.11k (50-11.8) = 42.4k the closest available high grade resistor with a low temperature coefficient of resistance should be used, and the three resistors should be matched to each other as closely as possible. in gen- eral, a 0.1% difference will introduce 1.7 arc minutes of addition- al error due to the effect on ratio relationship. the absolute value of the resistor is not critical. sin cos in the case of the resolver version (rdc), the equation is: r sig = 2.2k (new l-l level - standard unit l-l level) the calculated resistors are connected in series with s1 and s2 respectively. note only two resistors are required. the required resistor matching and its effect on accuracy, is the same as for a synchro input (see figure 4). the reference voltage treatment is similar, but the value select- ed is not critical. r ref = 2.8k (new ref - standard ref) here, even a 10% tolerance is adequate. sdc-630 r s1 s2 s3 r r r sig ref sig sig non-standard line-to-line level non-standard reference level figure 4. signal and reference scaling 14 lsb vel 13 0.015 0.002 0.015 0.01 0.01 0.10 (min) dia (typ) (max) (typ.) (tol. noncum.) 0.01 + + + + + + + - - - - - - - + 12 s4 11 s3 10 sdc-630 or sdc-632 or sdc-634 2.625 (66.68) dimensions in inches (mm). 3.125 (79.38) 0.26 (6.604) 0.21 (5.334) 2.2 (55.88) 0.25 (6.35) 0.430 (10.92) 0.040 (1.02) 0.20 (5.08) bottom view side view s2 9 s1 8 cb 7 inh 6 +15v 5 gnd 4 -15v 3 +5v 2 rl 1msb rh notes: 1. pin material is electrosoldered brass per mil-f-14072, m222. 2. case material is glass filled diallyl phthalate per mil-m-14, type sdg-f. 3. pins 13 and 14 are omitted for sdc-632, and pins 11, 12, 13, and 14 are omitted for sdc-630. 4. velocity output pin vel is present only if requested on special order. 5. pin s4 is present on resolver units, and omitted on synchro units. figure 5. sdc-630/632/634 mechanical outline
6 data device corporation www.ddc-web.com sdc-630/632/634 h-07/05-0 ordering information xxx -xxx -x-x-x-x reliability grade: r = enhanced reliability (note 1) accuracy: a = high accuracy version, 2.6 minutes (sdc-634 only) temperature range: 1 = -55c to +105c 3 = 0c to +70c signal input voltage and frequency: h = 90 v l-l , 400 hz (synchro or resolver) i = 90 v l-l , 60 hz (synchro only) m = 26 v l-l , 400 hz (resolver only) l = 11.8 v l-l , 400 hz (synchro or resolver) resolution: 634 = 14 bits 632 = 12 bits 630 = 10 bits input type: sdc = synchro rdc = resolver note 1. r version only available in -55c to 105c temperature range (option 1). enhanced reliability processing provides an additional 160 hour, 105 c burn-in and temperature cycling in accordance with mil-std-202. available sockets p/n 9010 = socket to barrel ends for soldering direct to socket pins p/n 9046 = socket to pin ends to solder socket to pcb p/n 9050 = socket to wire wrap pins ddc atp electrical test class 3 ipc-a-610 inspection / workmanship condition(s) method(s) test standard ddc processing for discrete modules/pc board assemblies
7 h-07/05-0 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-15 00 12-11, fax: +49-(0)89-15 00 12-22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u
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